FPTLOPT - An Automatic Transistor-Level Optimization Tool for GRM FPGA.

The FPGA circuit design usually adopts full-custom design method, it indicates that it is difficult to design and optimize an FPGA manually. So, we present FPTLOPT (FPGA Transistor-Level Optimization Tool) which supports a more complex FPGA architecture called general routing matrix (GRM) architecture, and also has higher-accuracy and higher-speed than COFFE [1]. To fit a more complex FPGA architecture, we use the regular matching method to automatically extract the circuits type and build the circuits netlist; To get the higher-accuracy, we predict the layout area by area model we build, then we precisely predict the layout post simulation delay by load model we build; To get the higher-speed, we devise the variable range greedy algorithm, to expanding range automatically. We also provide equalization kernel multi-thread acceleration that can change the thread number according to the current CPU hardware environment. The experimental results illustrate that FPTLOPT supports the optimization of GRM architecture and build the key sub-circuit netlist. Also, the area prediction is by maximum of 43%, the delay get from delay prediction is 28% more precise than the ones in COFFE. Besides, quickly gets the optimal transistor sizing results for different optimization objectives. For the same circuit, the optimization speed is 19.96 times faster than COFFE.