DOMIS - Dual-Bank Optimal Micro-Architecture for Iterative Stencils.

High-Level Synthesis (HLS) can achieve significant performance improvements through effective memory partitioning and meticulous data reuse. Many modern applications, such as medical imaging and convolutional layers in a CNN, mostly contain kernels where iterations can be reordered freely without compromising its correctness. In this paper, we propose an optimal micro-architecture that can be automatically implemented for simple and iterative stencil computations that utilizes only 2 banks to achieve fully parallel conflict memory accesses from single stage stencil kernels, while only requiring reuse buffers of size proportional to the kernel size to achieve an II of 1, irrespectively of the stencil geometry. We demonstrate the effectiveness of our micro-architecture by implementing it with a Kintex 7 xc7k160tg676-1 Xilinx FPGA and testing it with several stencil-based kernels found in real-world applications. On average, when compared with the mainstream GMP and SRC architectures our approach achieves approximately 30- 70% reduction in hardware usage, while improving performance by about 15%. Moreover, the number of independent memory banks required to accomplish conflict-free data accesses have dropped by more than 30% together with some increase in power consumption due to higher clock frequencies.