A High Resolution Time-To-Digital-Convertor Based On A Carry-Chain And Dsp48e1 Adders In A 28-Nm Field-Programmable-Gate-Array

A field-programmable-gate-array (FPGA) based time-to-digital-converter (TDC), which combines different types of delay chains in a single time measurement channel, is reported in this paper. A new TDC architecture is developed, and both a carry-chain and the DSP48E1 adders, which are integrated inside the FPGA chip, are employed to achieve high resolution time tagging. A single channel TDC has a 3.3 ps averaged bin size, a 5.4 ps single-shot precision, and a maximum sampling rate of 250 MSa/s. The differential-non-linearity of the single TDC channel is -3.3 ps/+24.1 ps, and the integral-non-linearity is within -10.4 ps/+68.6 ps. The TDC performance can be improved by using four TDC channels to measure one input signal, and a 3.4 ps single-shot precision can be obtained. Due to the implementation of the delicated TDC structure, only a small amount of digital resources is required to achieve the picosecond time measurement resolution. Therefore, the reported TDC architecture is suitable for multi-channel applications that require high time resolution measurements of multiple input signals.