High-Psrr, Low-Voltage Cmos Current Mode Reference Circuit Using Self-Regulator With Adaptive Biasing Technique

In this paper, we propose the low voltage CMOS current mode reference circuit using self-regulator with adaptive biasing technique. It drastically reduces the line sensitivity (LS) of the output voltage and the power supply voltage dependence of the temperature coefficient (TC). The self-regulator used in the proposed circuit adaptively generates the minimum voltage required the reference core circuit following the PVT (process, voltage and temperature) conditions. It makes possible to improve circuit performances instead of slightly increasing minimum power supply voltage. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65 nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, LS is reduced to 0.0065%/V under 0.8V < V-DD < 3.0V. TC is 67.6 ppm/degrees C under the condition that the temperature range is from 40 degrees C to 125 degrees C and VDD range is from 0.8V to 3.0V. The power supply rejection ratio (PSRR) is less than -80.4 dB when VDD is higher than 0.8V and the noise frequency is 100 Hz. According to the simulation results, we could confirm that the performances of the proposed circuit are improved compared with the conventional circuit.