Design of a cost-efficient controller for realizing a data-shift-minimized nonvolatile field-programmable gate array

Data shifting occupies an important function as a lookup table (LUT) circuit in a field-programmable gate array (FPGA), while its write energy is critical in magnetic tunnel junction (MTJ)-based nonvolatile FPGAs (NV-FPGAs). Minimizing data shifting by only permuting the order of the output data stream from the stored data in an LUT is an energy-efficient approach to solving the above problem. However, a concrete and energy-efficient controller design has not been discussed. In this paper, we propose a cost-efficient controller for realizing data-shift-minimized MTJ-based NV-FPGA. The hardware overhead in the proposed controller is significantly reduced by sharing the common functionality. In fact, the hardware overhead of the proposed controller is 68% smaller that of without hardware sharing. It is also demonstrated that the power consumption of the 512 bit shift register using MTJ-based LUT circuits with proposed controller is 88% smaller than that of SRAM-based one. (C) 2020 The Japan Society of Applied Physics