Efficient Diminished-1 Modulo (2(N )+1) Adder Using Parallel Prefix Adder

Parallel prefix adder (PPA) is the core component of diminished-1 modulo (2(n) + 1) adder structure. In this paper, group-carry selection logic based PPA design is proposed and it is free from redundant logic operations which otherwise present in the existing PPA design based on group sum selection logic. Further, the logic expression of pre-processing unit of PPA is also presented in a simplified form to save some logic resources. The proposed PPA design for bit-width 32-bit involves 26.1% less area, consumes 28.4% less power and marginally higher critical-path delay than the existing PPA design. An efficient diminished-1 modulo (2(n) + 1) adder structure is presented using proposed PPA design and modified carry computation algorithm of existing design. The proposed diminished-1 modulo (2(n) + 1) adder structure for bit-width 32-bit offers a saving of 25.5% in area-delay-product (ADP) and 24.1% in energydelay-product (EDP) than the best of the existing modulo adder structure.