Clock Gating Synthesis of Netlist with Cyclic Logic Paths

Gate-level clock gating is to synthesize clock gating structure (grouping of registers and extracting gating function of each group) from a netlist. We note that a simpler gating function can be derived from a cyclic logic path that connects the input and output of the same register. Another benefit comes from the fact that simplifying the cyclic paths using the derived gating function as don't-care is straightforward. A key problem in this approach is to extract a set of cyclic paths of each register, such that power consumption is minimized and circuit timing is left intact. Experiments demonstrate that power consumption is reduced by 49% on average of test circuits (with initial ungated netlist as a reference), while a sample previous gate-level clock gating achieves 34% of power saving.