A Design Framework For Hardware Approximation Of Deep Neural Networks
2019 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS (ISPACS)(2019)
摘要
For real-time edge AI applications, there is a need to implement deep neural networks (DNNs) in hardware for high speed. The trade-off between computing accuracy and hardware cost must be made during the implementation of hardware approximation. In this paper, we propose a design framework for DNN hardware approximation. The proposed framework provides a behavior model library of approximate logic circuits (e.g., approximate multipliers) for the designers to utilize them. Moreover, the proposed framework also supports the dynamic fixed-point arithmetic for hardware simulation. To save the required total bit width, we develop an integer length tuning method in the framework to maximize the computing accuracy under a constraint on the total bit width. Experimental results on ICNet show that the proposed framework can achieve high computing accuracy with small hardware cost.
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关键词
Neural Networks, Hardware Approximation, Hardware Simulation, Computing Accuracy, Bit Width, Design Methodology
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