Ldpc Code Design For Delayed Bit-Interleaved Coded Modulation

2019 IEEE INFORMATION THEORY WORKSHOP (ITW)(2019)

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摘要
This paper proposes a method to design low-density parity-check (LDPC) codes for delayed bit-interleaved coded modulation (DBICM). In the method, the code variable node (VN) degree distributions and the assignments of VNs with different degrees to DBICM subchannels are optimized via two cascaded differential evolution (DE) steps. In each step, to optimize VN degree distribution or channel assignment, a parity-check matrix is constructed, and the associated decoding threshold is calculated for each element in a generation. In constructing a parity-check matrix for each channel assignment, we propose a constraint PEG-like code construction method. Protograph-EXIT is employed to calculate the decoding threshold for each parity-check matrix. We apply the proposed method to construct irregular binary LDPC codes for both 16-QAM DBICM and BICM schemes. Simulation results demonstrate that the optimized LDPC codes are within 1 dB from the associated capacity limit at a bit error rate (BER) of 10(-6). Besides, the LDPC coded DBICM achieves an SNR gain of 0.5 dB to 0.1 dB over BICM counterparts at a code rate ranges from 0.25 to 0.5.
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关键词
Delayed bit-interleaved coded modulation, bit-interleaved coded modulation, low-density parity-check codes
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