Research on Area Modeling Methodology for FPGA Interconnect Circuits

Area models were proposed to estimate the implementation area in the early stage of chip design, and it is widely used in architectural exploration of advanced FPGA blocks and transistor sizing of FPGA interconnect circuits. Models in previous works have been proven to significantly overestimate the implementation area. This paper aims to propose area models more applicable to interconnect in FPGA, considering the features of actual layout more. Also, this paper compared the estimated area with the layout area of actual interconnect circuits in FPGA to check whether area models proposed are of high accuracy. The results showed that model errors of area models proposed in this paper for nine kinds of interconnect sub-circuits were all within ± 10% and much better than area models proposed in previous papers. It is concluded that this area model is more suitable for modern FPGA interconnect circuits.