Balance of memory footprint and runtime for high-density routing in large-scale FPGAs

The scale of modern FPGAs is expanding and applications on FPGA are becoming more and more complex. Applications requiring high-density routing in large-scale FPGA determine that CAD tools not only require large memory consumption, but also require long routing runtime. This paper proposes a method to describe the regularity of interconnect resources in CB/SB structure, and then applies a two-level template method to store the routing resource graph (RRG) which describes the detailed FPGA interconnect resources. This algorithm fully considers the high regularity of interconnect resources in large-scale FPGAs with CB/SB structure, memory footprint could be reduced. At the same time, RRG created by this method does not affect the routing search space, thus routing runtime will not change significantly. Implementation of the algorithm on VPR platform shows a memory reduction of 1.83X could be achieved at a routing runtime penalty of 1.07X.