Partitioning FPGA-Optimized Systolic Arrays for Fun and Profit

Long Chung Chan
Long Chung Chan
Gurshaant Malik
Gurshaant Malik
Nachiket Kapre
Nachiket Kapre

ICFPT, pp. 144-152, 2019.

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Abstract:

We can improve the inference throughput of deep convolutional networks mapped to FPGA-optimized systolic arrays, at the expense of latency, with array partitioning and layer pipelining. Modern convolutional networks have a growing number of layers, such as the 58 separable layer GoogleNetv1, with varying compute, storage, and data movemen...More

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