Hdc-Im: Hyperdimensional Computing In-Memory Architecture Based On Rram

Brain-inspired Hyperdimensional Computing (HDC) is a fast and robust classification algorithm, which works by mapping low-dimensional features to high-dimensional vectors and comparing distance in a high dimensional space. However, in traditional Von Neumann architecture, HDC causes high energy consumption because of large data movements between processor and memory. In this paper, we propose HDC-IM, a Hyperdimensional Computing-In-Memory architecture based on Resistive Random-Access Memory (RRAM), to boost the energy efficiency of HDC. HDC-IM puts computations in or near memory, which eliminates most of the data movements, providing a solution to reduce the energy consumption. In addition, to improve the computing parallelism, we use in-crossbar RRAM-based logic design to process encoding operation in HDC. The experimental results show that HDC-IM provides more than 100x speedup and higher energy efficiency compared with HDC on CPU. Moreover, in comparison with existing RRAM-based Neural Network accelerators, HDC-IM is more fault-tolerant taking into account RRAM device faults, achieving 20% higher accuracy than RRAM-based DNN on ISOLET dataset when 20% RRAM devices suffer from Stuck-At-Faults (SAFs).