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Xmss And Embedded Systems Xmss Hardware Accelerators For Risc-V

SELECTED AREAS IN CRYPTOGRAPHY - SAC 2019, (2020): 523-550

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Abstract

We describe a software-hardware co-design for the hash-based post-quantum signature scheme XMSS on a RISC-V embedded processor. We provide software optimizations for the XMSS reference implementation for SHA-256 parameter sets and several hardware accelerators that allow to balance area usage and performance based on individual needs. By ...More

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Author
Wen Wang
Wen Wang
Bernhard Jungk
Bernhard Jungk
Julian Wälde
Julian Wälde
Shuwen Deng
Shuwen Deng
Naina Gupta
Naina Gupta
Jakub Szefer
Jakub Szefer
Ruben Niederhagen
Ruben Niederhagen
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