New design of analog and mixed-signal cells using back-gate cross-coupled structure

Analog integrated circuits, in particular passive components, never follow the Moore's law. FDSOI (Fully Depleted Silicon On Insulator) technology allows to reduce the SCE (Short Channel Effect) and to design new mixed-signal topologies in order to remove passive component. To illustrate this SCE problem, a current mirror was chosen and a new design is proposed. First, a RO (Ring Oscillator) based on back-gate cross-coupled structure and complementary logic, has been designed, optimized and measured. Using the same technique, a current mirror is studied and finally implemented to a VCRO (Voltage Controlled RO). The concept is validated by simulations and measurements.