Evaluation of SET under Process Variability on FinFET Multi-level Design

Challenges were introduced in integrated circuits design due to the technology scaling. The evolution of integrated circuits has made them more susceptible to the radiation effects, besides increasing the manufacturing process variability, which can lead to circuits operating outside their specification ranges. Transistor arrangement influences the performance of logic cells; complex logic gates can be used to minimize area, delay and power. However, with the increasing relevance of nanometer challenges, it is necessary also to consider these factors at logic level design. This work explores different transistor arrangements for a set of logic functions at the layout level to evaluate the SET response under the process variability. The complex gate and the multi-level of NAND2 topologies, that implement the same function, were designed using the 7nm FinFET ASAP7 Process Design Kit. Results show that the multi-level topology is more robust to the radiation effects at both nominal conditions and considering the impact of process variability. The LETth value considering the multi-level topology is on average 55% higher than the values considering the complex topology. Moreover, all the logic functions analyzed independently of the topology are more sensitive to the SETs considering the impact of the process variability.