Reduction of process temperature for Si surface flattening utilizing Ar/H 2 ambient annealing and its application to SOI-MISFETs with bilayer HfN high-k gate insulator

We have investigated the reduction of the process temperature for the Si surface flattening process by annealing in Ar/H-2 ambient and its application to Si-on-insulator (SOI) metal-insulator-semiconductor field-effect transistors (MISFETs) with bilayer HfN high-k gate insulator. The surface rms roughness of 0.057 nm was realized for the p-Si(100) substrates by the annealing at 925 degrees C/10 min in Ar/1.0%H-2 ambient. Although slip-line defects were observed in the isolated SOI region after the optimized flattening process, the device characteristics of the fabricated SOI-MISFETs with HfN1.3/HfN1.1/Si(100) bilayer gate insulator were found to have been improved by the surface flattening utilizing Ar/1.0%H2 annealing. (C) 2019 The Japan Society of Applied Physics