A Low-Computation-Cycle Design Of Input-Decimation Technique For Ridft Algorithm

In this paper, a low-computation-cycle and energy-efficient design of input-decimation technique for the recursive inverse discrete Fourier transform (RIDFT) algorithm is proposed for the high-speed broadband communication systems. It is crucial that the input-decimation technique is presented to decrease the number of input sequences for the recursive filter so that the computation cycle of RIDFT can be shortened to meet the computing time requirement (3.6 mu s). Therefore, the input-decimation RIDFT algorithm is able to carry out at least 55.5% reduction of the total computation cycles compared with the considered algorithms. Holding the advantages of input-decimation technique, the computational complexities of the real-multiplication and -addition are reduced to 41.3% and 22.2%, respectively. Finally, the physical implementation results show that the core area is 0.37 x 0.37 mm(2) with 0.18 mu m CMOS process. The power consumption is 5.16 mW with the supply voltage of 1.8 V and the operating clock of 40 MHz. The proposed design can achieve 258 million of computational efficiency per unit area (CEUA) and really outperform the previous works.