A Wr-3 Band Distributed Frequency Doubler With A Differential Quasi-Cascode Structure

This paper presents a WR-3 band distributed frequency doubler implemented in a 250-nm InP HBT technology. Three doubler unit cells are combined together with input and output transmission lines in a distributed way to achieve a wide bandwidth. A differential quasi-cascode pair is proposed for each unit cell design, which enables bandwidth extension and chip-size reduction. The distributed doubler exhibits measured peak power and conversion gain of 2.2 dBm and -6.5 dB, respectively, at 276 GHz. The doubler maintains high output power above -5 dBm from 225 to 320 GHz, which covers almost the entire WR-3 band. Due to the proposed compact distributed structure, the chip occupies only 0.23 mm(2) including all probing pads.