Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction

2019 Symposium on VLSI Technology(2019)

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摘要
In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.
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关键词
reliability,logic technology nodes,gate extension scaling,gate-cut-last integration scheme,replacement metal gate module,integration process,gate extension length,parasitic capacitance reduction,conventional gate cut method,novel CT-in-RMG process,performance variation,end fin
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