Toward Reliable Extraction of the Properties of Border Traps in Lateral GaN Power MOSFET with a Distributed Network Model

Robust gate dielectric and dielectric/semiconductor are highly desired for GaN power MOS devices, while the trapping effect of the border traps close to the MOS interface could lead to reliability issues in those devices. In this paper, a complete model for border traps in lateral GaN MOS diode is proposed based on a distributed network of the border traps and channel resistance. We show that excluding the effect of channel resistance is critical for accurate calculating the distribution of border traps in lateral devices with low channel mobility, such as GaN and SiC MOS devices. The proposed model agrees well with the measured frequency dependent capacitance and conductance curves of Al ₂ O ₃ /GaN MOS diode in a gate recessed normally-off GaN power MOSFET. The new insight derived from the impedance dispersion characteristics of lateral MOS devices is critical for quantitative analysis of the quality of III-V lateral MOS structures.