Standard Cell Optimization for Ultra-Low-Voltage Digital Circuits

Sub-/near-threshold regions have been demonstrated to be attractive operation regions to achieve either the minimum energy consumption or the optimal energy efficiency for digital integrated circuits. The development of digital standard cell library suitable for ultra-low voltages is a critical enabler for sub-/near-threshold region operations. A variety of optimization methods are proposed in this paper for the design of ultra-low-voltage standard cells. The statistics of the transistor currents at ultra-low voltages are explored in this work, while the technology coherence is considered. Transistor size optimization as well as body biasing is employed to enhance the switching and area efficiency of the transistors. With the proposed optimization methods, both the delay and power consumption are reduced significantly for test circuits, as compared to using the traditional standard cell library that is provided by the Foundry in a 65-nm CMOS technology.