Energy Efficient Clock Distribution with Low-Leakage Multi-Vt Buffers

A new low power clock distribution network with multi-threshold-voltage (multi-V _t ) repeaters is presented in this paper. A repeater circuit with two inputs and two outputs is employed for suppressing leakage currents in gated clock distribution networks. The standby leakage power consumption is reduced by 50.93% with the proposed clock tree as compared to the conventional 3 level H-tree operating with a power supply voltage of 0.8V in a 45nm CMOS technology. In addition to providing significant power savings in idle clock distribution networks, the proposed circuit technique also lowers the total energy consumption of partially active networks. Depending on the percent of segments that experience local clock gating, the total energy consumed by the proposed clock network is 6.78% to 80.43% lower as compared to the conventional clock tree with a power supply voltage of 0.4V and a clock frequency of 10MHz.