Effect of Temperature on the Electrical Characteristics of 4H-SiC Planar n/p-Type Junctionless FET: Physics Based Simulation

In this paper, we have explored planar junctionless FET (JLFET) in 4H-SiC as a potential device for future industrial applications. We show the differences in static electrical characteristics (Id-Vg, Id-Vd, subthreshold current and Ion/Ioff ratio) between n and p-type JLFETs whilst varying the lattice temperature (T) from 300 K to 700 K using 2D numerical simulations. The oxide-SiC interface traps have shown minimum influence on the device current conduction characteristics. For the same one-micron channel length and an equal area of cross-section, the p-type JLFET exhibits lower off-state current (Ioff) leading to higher Ion/Ioff ratio, a higher threshold voltage (VTH) and lower subthreshold current in comparison to the n-type JLFET.