Poster Abstract: A Template-Based Framework For Generating Network Processor In Fpga

Domain specific language (DSL) like P4 is widely used in networking field for the high productivity. However, it is difficult to translate P4 procedures to low level ones running on Field Programmable Gate Array (FPGA) automatically, which is used to prototype customized packet processing or in application specific domain. In this paper, we proposed a template-based framework for generating network processor with match-action architecture by translating P4 procedures to VHDL programs automatically. The framework extracts the function modules and the corresponding parameters from P4 programs firstly. These function modules will be mapped to pre-build efficient VHDL templates for high performance. Finally, the selected templates will be instantiated and scheduled to form a fully processor according to the requirements. Experiments show that the generated processor is not only high throughput, but also low latency.