Enhanced 3D Implementation of an Arm^® Cortex^®-A Microprocessor

High-density 3D techniques (such as wafer bonding and monolithic-3D) show tremendous promise in reducing interconnect lengths and relieving 2D congestion. We propose an enhanced 3D implementation methodology and use it to design an Arm Cortex-A microprocessor in 3D. The methodology is fully integrated and tested using commercial EDA tools and incorporates all physical IP needed to implement modern microprocessors. The resulting 3D implementation consists of two parts, 1) a multi-tier co-placement approach for enhanced placement quality, 2) integration of 3D SRAMs for improved microprocessor PPA. Compared to the 2D baseline, our implementations show an overall area reduction of 8.5% and can either achieve an 18% peak frequency uplift at iso-power or a 41% power reduction at near iso-performance (-3% frequency).