A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy

Battery-operated sensing systems have very low activity rates and power down most blocks during inactive periods to save power. During active periods, these energy-constrained systems typically operate at near or sub-threshold voltage for maintaining energy efficiency. Therefore, these ultra-low energy systems require a read-only, non-volatile code memory that can be accessed at sub-threshold voltage. ROM is the most energy efficient read-only non-volatile memory. A conventional compiler ROM cannot work reliably in near threshold regions of operation due to lack of read margin. As a result, for energy constrained IoT systems, the ROM design needs to support reliable read at low operating voltages, and a speed degradation at low voltages which is at par with logic circuits, to avoid the ROM from limiting the system performance. This paper proposes a sub-threshold ROM that addresses both reliability and performance issues by 1) Using a switched source-line (SSL) to nullify Ioff and improve read margin, 2) Compensating performance degradation caused by SSL using a novel data encoding scheme and by using unused `0' bit-cell transistors to provide local pull-down paths, 3) Tackle variation-based performance degradation by optimizing bit-cell sizing for sub-threshold, and 4) Providing a fine-grained threshold voltage adjustment technique for trading off performance improvement with leakage degradation by using a novel INverse Width Effect (INWE) bit-cell layout. The proposed SSL sub-threshold ROM is fabricated in 65nm technology, with an 8kB capacity, and a V _min of 0.3V. At 0.4V, it has a read speed of 1.1MHz and an access energy of 47fJ/bit.