Auto-Calibrating Tdc For An Soc-Fpga Data Acquisition System

In this paper, an FPGA-based plain delay line time-to-digital converters (TDC) is presented, together with a theoretical model on its timing properties. The TDC features an automated calibration system implemented in the on-chip processor of an SoC-FPGA, uses a low amount of FPGA resources and is therefore suitable for applications requiring a high number of channels, such as time-of-flight positron emission tomography (PET). We first investigated the importance of calibration and validated the theoretical model on the TDC timing properties. Finally, the device has been embodied into a two channel PET acquisition system and tested. We found the calibration essential to obtain a good time resolution (38-ps FWHM in comparison with a 78-ps FWHM obtained with the uncalibrated device). The model we developed is able to predict the TDC timing properties. They are shown to be related to the fundamental parameters of the used FPGA technology. In particular, the best achievable time resolution of this specific architecture (plain tapped delay line on FPGA) is set to about 30 ps by the sum of the setup and hold times of the registers in the FPGA. The timing resolution of the two-channel setup is about 118 ps.