Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning

Test infrastructure of High-Density Three-Dimensional Integrated Circuits (HD 3D-IC) present a new test challenges because of the high interconnect density and the area cost for test features. In this work, we firstly present a pre-analysis of the testability of HD 3D-IC; we define the minimum acceptable 3D pitch value for a given technology to ensure the circuits testability. Afterwards, we propose an optimized DFT architecture allowing pre-bond and post-bond test for SRAM/Logic HD 3D-IC in line with the ongoing IEEE P1838 standard.