A Lean, Low Power, Low Latency Dram Memory Controller For Transprecision Computing

Energy consumption is one of the major challenges for the advanced System on Chips (SoC). This is addressed by adopting hetero-geneous and approximate computing techniques. One of the recent evolution in this context is transprecision computing paradigm. The idea of the transprecision computing is to consume adequate amount of energy for each operation by performing dynamic precision reduction. The impact of the memory subsystem plays a crucial role in such systems. Hence, the energy efficiency of a transprecision system can be further optimized by tailoring the memory subsystem to the transprecision computing. In this work, we present a lean, low power, low latency memory controller that is appropriate for transprecision methodology. The memory controller consumes an average power of 129.33mW at a frequency of 500MHz and has a total area of 4.71mm(2) for UMC 65nm process.