Efficient Methodology of Sampling UVM RAL During Simulation for SoC Functional Coverage

Register files verification represent critical part of any digital design verification process. Many techniques had appeared in order to model register files and memories in the verification environment. One of the most powerful ways to model memories and register files is using Register Abstraction Layer (RAL) which is part of the Universal Verification Methodology (UVM). This paper will go through the process of UVM Register model generation with its coverage model using Synopsys tools. We propose an efficient methodology to automatically update the register model with the changes of the hardware registers using a backdoor technique, especially the read-only registers in order for that register model to be processed for checking and coverage in an efficient way. The proposed methodology has strong flexibility in frequent design specification changes. Template based code generation gives high level maintainability. The proposed functional coverage technique is applied to beat performance degradation and enhance the simulation.