A 3 Gbps/Lane Mipi D-Phy Transmission Buffer Chip

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences（2019）

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摘要

A 3 Gbps/lane transmission buffer chip including a high-speed mode detector is proposed for a field-programmable gate array (FPGA)-based frame generator supporting the mobile industry processor interface (MIPI) D-PHY version 1.2. It performs 1-to-3 repeat while buffering low voltage differential signaling (LVDS) or scalable low voltage signaling (SLVS) to SLVS.

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关键词

transmission buffer chip,LVDS,SLVS,MIPI D-PHY,FPGA-based frame generator

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