Fast Lagrangian Relaxation Based Multi-Threaded Gate Sizing Using Simple Timing Calibrations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(2020)

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摘要
Accurate delay analysis with distributed RC delay can be computationally expensive, and can contribute the majority of the total runtime for gate sizers. Recent works have shown that Lagrangian relaxation (LR)-based gate sizers have produced designs with the lowest power on average. But they are also very slow due to a large number of expensive timing updates spread across several tens of iteratio...
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关键词
Logic gates,Delays,Runtime,Capacitance,Computational modeling,Optimization
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