Fault-tolerant Systolic Array Based Accelerators for Deep Neural Network Execution
IEEE Design & Test of Computers(2019)
摘要
Editor’s note: Systolic array is embracing its renaissance after being accepted by Google TPU as the core computing architecture of machine learning acceleration. In this article, the authors propose two strategies to enhance fault tolerance of systolic array based deep neural network accelerators. —Yiran Chen, Duke University
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关键词
Fault tolerance,Fault tolerant systems,Neural networks,Computer architecture,Clocks,Google
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