Analysis of a failure mechanism occurring in SiGe HBTs under mixed-mode stress conditions

This paper presents an investigation of hot carrier degradation in advanced SiGe HBTs. This failure mechanism is observed under mixed mode stress conditions. Its physical location is examined through DC measurements from 2D transistors $(\mathrm{L_{E}} > > \mathrm{W}_{\mathrm{E}})$ with different emitter width WE. TCAD simulations were performed to confirm its physical origin and location. The methodology permits to identify the origin of the degradation mechanism located at the emitter-base spacer interface. It is based on the scalable analysis of the DC characteristics measured after stressing the devices during 10 000s under mixed mode (MM) stress conditions. This study confirms the mechanism responsible of the MM degradation for SiGe HBTs.