Circuit Under on-chip-inductor structure (CUL) for the areal size reduction of Si-based RF circuit

A novel Circuit Under on-chip-inductor structure (CUL) including high-Q inductor (Q peak > 19) formed in the redistribution layer (RDL) is proposed to reduce the chip-size of RF embedded MCUs/SoCs. A design methodology for the CUL implementation without degrading RF performance is also discussed. Measured phase noise of LC-VCO with proposed CUL structure suggests that a footprint can be effectively reduced without compromising performances. We estimate that PLL size can be reduced by 30% with the proposed technology.