HCI Improvement on 14nm FinFET IO Device by Optimization of 3D Junction Profile

This paper investigates Hot Carrier Injection (HCI) behavior on 14nm FinFET Input/Output (IO) device. Junction profile at drain extension region is a key factor in improving HCI degradation. A scheme of optimized lateral electric field and less impact ionization at the drain extension region is required for reliable and robust HCI performance of IO NFET. In this paper we show an optimal scheme of implantation condition verified with robust HCI reliability on high volume production silicon wafers. It is also confirmed that the proposed condition does not impact both device performance and chip yield.