High Throughput/Gate FN-Based Hardware Architectures for AES-OTRMarkRei UenoNaofumi Homma[0]Tomonori IidaKazuhiko Minematsu[0]international symposium on circuits and systems, 2019.Cited by: 1|Bibtex|Views8|LinksEI Code: Data: Full Text (Upload PDF)PPT (Upload PPT)Upload PDFUpload PPTYour rating :0 TagsCommentsSubmit
