An Approach To Compensate For Capacitor Mismatches In Sar Adc Using Multiple Comparisons

This paper presents a new approach to compensate for mismatches in capacitor array of a successive-approximation-register (SAR) analog-to-digital converter (ADC). The proposed approach employs multiple comparisons per bit cycle before making a decision. Instead of taking the majority vote as has been done in existing work, different threshold values are used to compensate for the transition level reference voltage errors caused by capacitor mismatches. A closed-form expression of the effective comparator noise as a function of different threshold value shifts and number of votes is derived. Simulation results of an 8-bit SAR ADC show that the proposed scheme achieves near ideal ENOB and SFDR performance.