24.3 A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology

Embedded SRAM is a key component that typically determines the overall processor performance. A fully customized SRAM requires a long design cycle; hence, an SRAM compiler that can provide a wide range of user-specified SRAM designs, by utilizing predefined leaf cells, is widely used. An SRAM compiler must exhibit robustness across a wide range of voltage and temperature conditions. On top of optimizing power and performance for a variety of applications, a compiler also enables dynamic voltage and frequency scaling. However, the temperature and voltage sensitivity of an SRAM bitcell limits its voltage and temperature operating range, thus significantly degrading read and write stability. Several approaches to improve SRAM stability have been proposed [1]–[6]; however, the WL under-drive (WLUD) read-assist technique is the most widely used: owing to its simple architecture, and smaller power and area overhead [12]. However, this approach reduces the WL voltage at voltage and temperature conditions that do not require WLUD; thus, degrading read speed and the write margin (WRM).