24.2 A 7nm 2.1ghz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue
2019 IEEE International Solid-State Circuits Conference - (ISSCC)（2019）
Key words
DP-SRAM bitcell,DP-SRAM design,WL-RC optimization,dummy-read-recovery circuitry,continued transistor scaling,wire routing resistance,capacitance,SRAM design difficulties,circuit design,single-port SRAM,process scaling,read-disturb-write problem,dual-port SRAM,worst-case operation,asynchronous clocks,simultaneous read and write operations,read-disturb-write issue,RC degradation,size 7.0 nm,frequency 2.1 GHz
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