A variation tolerant data dependent clock gating approach for PSN attenuated low power digital IC

The evolution of semiconductor industry has brought in high current flow across the power rails (‘Vdd’ and ground) of digital integrated circuits (IC) encapsulated by the modern chip packages. This instigates the uncontrollable generation of Power Supply Noise (PSN), along with dynamic and static power dissipation across the chip package. There have been several attempts to control this PSN; but it is the clock gating (CG) technique which is found to be efficient for the purpose. Though the primitive CG schemes are effective in managing the dynamic power dissipation, their performance to alleviate the static power and PSN is limited to certain extent. Therefore in this paper, we introduce a new and compact Data-Dependent CG (DD–CG) scheme which can possibly be the savior against both static and dynamic power as well as the PSN. The performance of the new DD–CG is tested over state-of-the-art master–slave flip-flop (MS–FF) and ISCAS’89 benchmark for 90 nm General Process Design Kit (GPDK) technology using the platform of Cadence Virtuoso® at supply voltage of 1.1 V and 5 GHz clock. It is observed that the new DD–CG based MS–FF smartly reduces the PSN individually by 22.19%, 18.99% and 46.92% in contrast to the prior-arts like NC2MOS–CG, LB–CG and no–gated peer. Accordingly, the static power is reduced by 20.63%, 17.79% and 33.61% and the dynamic power is also reduced by 25.14%, 21.24% and 61.57%. To justify the scalability of the design, we have also tested it for the lower process technologies like 65 nm, 40 nm and 28 nm UMC (United Microelectronics Corporation).