Voltage Transfer Characteristic Matching By Different Nanosheet Layer Numbers Of Vertically Stacked Junctionless Cmos Inverter For Sop/3d-Ics Applications
2018 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)(2018)
摘要
For the first time, CMOS inverters with different numbers of vertically stacked junctionless (JL) nanosheets (NSs) are demonstrated. All fabrication steps were below 600 degrees C, and 8-nm thick poly-Si NSs with smooth surface roughness were formed by a dry etching process. Compared to single channel devices, stacked n/p-channel FETs exhibit higher on-current with low leakage current. Furthermore, a common-gate process was performed for the fabrication of CMOS inverters. By adjusting the NS layer numbers for n/pFETs, respectively, the voltage transfer characteristics (VTCs) of the CMOS inverter can be matched much better to reduce the noise margin due to on-current matching without area penalty. This work experimentally demonstrates a new configuration of CMOS inverters on stacked NSs, which is promising for System-on-Panel (SoP) and 3D-ICs applications.
更多查看译文
关键词
stacked n/p-channel FET,poly-Si NS,SoP/3D-IC applications,nanosheet layer numbers,smooth surface roughness,system-on-panel,NS layer numbers,low leakage current,single channel devices,dry etching process,vertically stacked junctionless nanosheets,vertically stacked junctionless CMOS inverter,voltage transfer characteristic matching,Si
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要