Evaluation of wireless network-on-chip architectures with microchannel-based cooling in 3D multicore chips

Three-dimensional multicore Integrated Circuits (3D ICs) with Network-on-Chip (NoC) based interconnections provide promising solutions to the challenges of footprint, device density and energy cost of on-chip communication. However, the increase in power density in 3D ICs due to reduced footprint aggravates the thermal issues in the chip. Liquid cooling through microfluidic channels can provide cooling capacities required for effective management of chip temperatures in 3D ICs. However, pumping liquid through the microchannels can cause high pressure-drops causing structural instability in the chip. In order to reduce the pressure drops and provide adequate cooling capability, the height and width of the microchannels needs to be increased. This reduces the available floor area of the 3D IC to place and route Through Silicon Vias (TSVs) for data signals through the microchannel walls making the co-design of microchannels and TSVs challenging. Hence, in this paper we evaluate the advantages and discuss the trade-offs of realizing the vertical interconnects for data communication across the cooling layers with on-chip wireless interconnects. We present optimal design for microchannels for cooling 3D multicore chips from a combined perspective of thermal efficiency, flow rate and pressure drop. Based on these designs we discuss the potential of wireless interconnects and demonstrate that a 3D wireless NoC is capable of establishing data communication across the cooling layers with lower energy consumption.