Synchronous Adaptive Resolver-to-Digital Converter for FPGA-Based High-Performance Control Loops

This paper deals with a gain scheduling synchronous demodulation scheme useful to obtain speed and position measurements from resolver position sensors. The proposed algorithm is devoted to a field-programmable gate array implementation in order to provide the elaborated information for very low latency control loops. The presented design allows getting accurate estimations in a wide range of rotational speeds without requiring costly off-the-shelf integrated circuits and leads to higher accuracy at low speed if compared to commercial solutions. To this purpose, the resolver excitation circuit has been simplified working directly with a square wave signal, and the resolver frequency behavior due to the nonsinusoidal excitation has been considered.