Gate Bias Modulation for Doherty Power Amplifier

In this paper we demonstrate performance enhancements of peak power and efficiency of a Doherty amplifier through the application of Gate Bias Modulation (GBM) of the peaking amplifier. To prove out the architecture, a symmetrical Doherty amplifier has been designed around two NXP LDMOS power transistors targeting frequencies from 2110 MHz to 2170 MHz. Measured performance indicates that GBM offers more than a 1 dB increase in peak power while also improving efficiency by 3 percentage points. Further, we show that a GBM Doherty amplifier can be linearized using Digital Pre-Distortion (DPD) to achieve better than 52 dB adjacent channel power ratio when amplifying a three carrier-long term evolution (LTE) signal.