Comprehensive Study of ESD Design Window Scaling Down to 7nm Technology Node
2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)(2018)
摘要
ESD design window for mainstream bulk and SOI planar/FinFET technologies across 350nm7nm node are compared for the first time. 100ns TLP and 1ns vfTLP characteristics of V
gox
, and V
t1
, and I
t2
of various logic and I/O FETs are presented anddiscussed. Expanding the design window by utilizing series resistance within I/O driversis discussed.
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关键词
ESD design window scaling,SOI planar/FinFET technologies,size 7.0 nm,time 100.0 ns,time 1.0 ns,size 350.0 nm
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