Comprehensive Study of ESD Design Window Scaling Down to 7nm Technology Node
electrical overstress electrostatic discharge symposium, 2018.
ESD design window for mainstream bulk and SOI planar/FinFET technologies across 350nm7nm node are compared for the first time. 100ns TLP and 1ns vfTLP characteristics of V gox , and V t1 , and I t2 of various logic and I/O FETs are presented anddiscussed. Expanding the design window by utilizing series resistance within I/O driversis dis...More
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