Leakage Aware Si/Sige Cmos Finfet For Low Power Applications

Gen Tsutsui,Curtis Durfee,Miaomiao Wang,Aniruddha Konar,Heng Wu,Shogo Mochizuki,Ruqiang Bao,Stephen Bedell, Juntao Li,Huimei Zhou,Daniel Schmidt, Chun Ju Yang,James Kelly,Koji Watanabe, Theodore Levin,Walter Kleemeier,Dechao Guo,Devendra Sadana,Dinesh Gupta,Andreas Knorr,Huiming Bu

2018 IEEE SYMPOSIUM ON VLSI TECHNOLOGY（2018）

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摘要

Leakage in Si/SiGe CMOS FinFET is examined. Si cap passivation effectively improves SiGe pFET D-it, subthreshold slope, and mobility, which improves pFET DC performance by 20%. SiGe GIDL is higher than Si by a factor of 9, though GIDL is limited to 50pA/um. SiGe GIDL reduction knobs to meet Si counterpart are demonstrated. The results open the door to the next stage of Si/SiGe CMOS FinFET such as low power and low leakage applications.

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关键词

low power applications,subthreshold slope,pFET DC performance,low leakage applications,GIDL reduction,silicon cap passivation,leakage aware CMOS FinFET,current 50.0 pA,Si-SiGe

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