True 7nm Platform Technology Featuring Smallest Finfet And Smallest Sram Cell By Euv, Special Constructs And 3rd Generation Single Diffusion Break

Wc Jeong, S. Maeda,Hj Lee,Kw Lee,Tj Lee, Dw Park, Bs Kim, Jh Do, T Fukai, Dj Kwon,Kj Nam,Wj Rim, Jang,Ht Kim,Yw Lee,Js Park, Ec Lee, Dw Ha,C.H. Park,H.-J. Cho,S.-M. Jung, H.K. Kang

2018 IEEE SYMPOSIUM ON VLSI TECHNOLOGY(2018)

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摘要
7nm platform technology that takes full advantage of EUV lithography was developed, where EUV was straightforwardly used for single patterning of MOL and BEOL, not just as a means for cutting of SADP/SAQP. The combination of 27nm fin pitch (FP) and 54nm contacted poly pitch (CPP) as well as the high density SRAM cell size of 0.0262 um(2) is the smallest in the reported FinFET platform. Further scaling is secured with special constructs and the 3rd generation single diffusion break. Full working of 256M bit SRAM and large-scale logic test chip was demonstrated with guaranteed reliability.
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关键词
smallest SRAM cell,EUV lithography,single patterning,high density SRAM cell size,large-scale logic test chip,fin pitch,contacted poly pitch,FinFET platform,3rd generation single diffusion break,true platform technology,reliability,MOL single patterning,storage capacity 256.0 Mbit,size 7 nm
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