Multiple Workfunction High Performance Finfets For Ultra-Low Voltage Operation

M. Togo, R. Asra,P. Balasubramaniam,X. Zhang,H. Yu,S. Yamaguchi, E. Geiss, H. S. Yang, B. Cohen,H-C. Lo, O. Hu, H. Lazar, O. Kwon,D. Burnett, J. Versaggi, E. Banghart,M. K. Hassan,E. Bazizi,L. Pantisano,J. G. Lee, S. B. Samavedam, D. K. Sohn

2018 IEEE SYMPOSIUM ON VLSI TECHNOLOGY（2018）

引用 5|浏览20

暂无评分

摘要

A multiple workfunction (multi-WF) integration technology was developed for ultra-low voltage operation in high performance FinFETs. It is essential to solve three key issues in the multi-WF process, a) short channel effect (SCE) degradation due to removing halo implants b) gate resistance increase due to multi-WF stack, and c) gate dielectric reliability degradation due to additional patterning. In this study, we resolve these issues through the combination of junction engineering and workfunction metal (WFM) boolean engineering in long channel (LC) and short channel (SC) devices for SCE, WFM stack optimization for gate resistance, and HK interface optimization for reliability. In logic devices, 15/13% N/PFET DC and 14% AC performance were improved without SCE or reliability degradation. In SRAM devices, 43% Vt mismatch (Vtmm) improvement resulted in record Vmin yield down to 0.4V on 128Mb 0.064 mu m(2) SRAM array.

查看译文

关键词

gate resistance,AC performance,multiple work function high performance FinFETs,SCE degradation,halo implant removal,work function metal Boolean engineering,gate dielectric reliability degradation,long channel devices,short channel devices,logic devices,HK interface optimization,SRAM devices,reliability degradation,WFM stack optimization,junction engineering,multiWF stack,short channel effect degradation,multiWF process,integration technology,ultra-low voltage operation,voltage 0.4 V,storage capacity 128 Mbit

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要